The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. Particularly, the present invention is concerned with a technique applicable effectively to a semiconductor integrated circuit device with both high breakdown voltage MISFET (Metal Insulator Semiconductor Field Effect Transistor) and low breakdown voltage MISFET formed on the same semiconductor substrate, as well as a method of manufacturing the same.
In Japanese Unexamined Patent Publication No. 2002-170888 (Patent Literature 1) is disclosed a technique for increasing the drain breakdown voltage by forming an electric field relaxing layer around source and drain regions of a high breakdown voltage MISFET.
[Patent Literature 1]
Japanese Unexamined Patent Publication No. 2002-170888